1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to mask-programmable read-only memory (mask-ROM).
2. Prior Arts
Mask-programmable read-only memory (mask-ROM) refers to those types of memories into which data are written during manufacturing, preferably during the lithographic steps. Three-dimensional mask-programmable read-only memory (3D-MPROM) is a mask-ROM comprising a plurality of mask-ROM levels stacked above and coupled to a semiconductor substrate. Among all types of mask-ROM, 3D-MPROM has a very large capacity and a very low cost.
U.S. Pat. No. 5,835,396, issued to Zhang on Nov. 10, 1998, and U.S. Pat. No. 6,624,485, issued to Johnson on Sep. 23, 2003, disclose examples of 3D-MPROM. FIG. 1 illustrates a typical 3D-MPROM. It comprises a semiconductor substrate 0s and a 3D-MPROM stack 0. The semiconductor substrate 0s comprises transistors, which form the peripheral circuit for 3D-MPROM. The 3D-MPROM stack 0 is stacked above the substrate 0s. In this example, it comprises two memory levels: 100 and 200; and the memory level 200 is stacked above the memory level 100. Each memory level (e.g. 100) comprises a plurality of address lines (e.g. 20a, 20b, 30a . . . ) and memory cells (e.g. 1aa, 1ab . . . ). Contact vias (e.g. 30av, 30av′) couple memory levels (e.g. 100, 200) to the substrate 0s. 
Most 3D-MPROM's disclosed in prior arts are binary, i.e. memory cells have two states: ‘1’ and ‘0’: state ‘1’ conducts current, whereas state ‘0’ does not. Each binary cell can store one bit of data.
As illustrated in FIG. 2A, a ‘1’ 3D-MPROM cell 1aa comprises an upper address line 20a, a ROM-layer 3a and a lower address line 30a. The ROM-layer 3a comprises a quasi-conduction layer 5, which is a non-linear resistor and conducts more current in one direction than in the other direction. The quasi-conduction layer 5 is generally a diode. Here, it is a p-i-n diode, including a p-layer 12, an i-layer 14 and an n-layer 16. It could also be other diodes, such as p-n diode or Schottky diode. Because there is a contact 18 in the insulating dielectric 11, a read current can be sensed in the lower address line 30a when a read voltage is applied to the upper address line 20a. This corresponds to the state ‘1’.
As illustrated in FIG. 2B, a ‘0’ 3D-MPROM cell 1ba comprises an upper address line 20b, a ROM-layer 3b and a lower address line 30a. The ROM-layer 3b further comprises an insulating dielectric 11. Because there is no contact in the insulating dielectric 11, no read current can be sensed in the lower address line 30a when a read voltage is applied to the upper address line 20b. This corresponds to the state ‘0’.
Besides binary, 3D-MPROM can be N-ary (N is a positive integer and N>2), i.e. memory cells have N states and cells in different states have different current-voltage (I-V) characteristics. Each N-ary cell can store b bits of data, namely b-bit-per-cell (bpc). Here, b=log2(N) and b can be an integer or a non-integer. U.S. Pat. No. 7,633,128, issued to Zhang on Dec. 15, 2009, and U.S. patent application Ser. No. 12/477,912, filed by Zhang on Jun. 4, 2009, disclose examples of N-ary 3D-MPROM. They include geometry-defined N-ary 3D-MPROM and junction-defined N-ary 3D-MPROM.
In a geometry-defined N-ary 3D-MPROM, cells in different states have different structures, e.g. different cell geometries. As illustrated in FIG. 2C, a geometry-defined cell 1ca comprises an upper address line 20c, a ROM-layer 3c and a lower address line 30a. The ROM-layer 3c further comprises an insulating layer 11, a partial contact 18′ and a quasi-conduction layer 5. Compared with FIG. 2A, the partial contact 18′ in the insulating layer 11 only partially couples the upper address line 20c to the quasi-conduction layer 25. Accordingly, memory cell 1ca has a different I-V characteristic than memory cell 1aa. 
In a junction-defined N-ary 3D-MPROM, cells in different states have different junctions, e.g. different doping profiles. As illustrated in FIG. 2D, a junction-defined cell 1da comprises an upper address line 20d, a ROM-layer 3d and a lower address line 30a. The ROM-layer 3d has a similar structure as the ROM-layer 3a in cell 1aa (FIG. 2A), but its diode 5′ has a different doping profile than diode 5. This can be implemented by an extra implant. Accordingly, memory cell 1da has a different I-V characteristic than cell 1aa. 
The present invention makes further improvements to N-ary 3D-MPROM. By increasing the range of modulation for the cell I-V characteristics (e.g. to ˜4.5V or more), large bit-per-cell (e.g. 4-bpc) can be achieved. Accordingly, the present invention discloses a large bit-per-cell 3D-MPROM (3D-MPROMB).